EUV application, material and structure innovation, and reliability problem solving important
SK Hynix President Lee Seok-hee introduced the direction of mid- to long-term memory technology development.
President Lee served as a keynote speaker at the International Reliability Symposium (IRPS) of the International Institute of Electrical and Electronics Engineers (IEEE) held on the 22nd. “We will evolve the memory technology.”
The market introduced that in order to make a process DRAM of 10 nanometers or less, it is necessary to overcome the limitations of patterning (lithography), maintain cell capacitor capacity, and develop a low-resistance wiring technology. SK Hynix emphasized that it is currently working on materials, defect management, and photoresist development by introducing an extreme ultraviolet (EUV) process. It also explained that it is expanding the cell capacity by reducing the thickness of the dielectric deposited on the capacitor, applying new materials, and structural innovation.
For automotive semiconductors, he said it is important to solve’soft errors’. Resolving soft errors requires design improvements, but at the same time increases cost. President Lee said, “We are developing a process that improves the design while reducing the cost burden.”
The technical challenges in the NAND flash field are summarized as △HARC (High Aspect Ratio Contact) etch (etching) technology △Securing cell dielectric properties △Film stress problem solving.
President Lee said, “For stacking more than 600 layers in NAND flash, an etching technology that can realize a high aspect ratio is required.” ALD) technology is being introduced.”
In addition, he added that in order to solve the phenomenon that the wafer is warped or pushed (film stress problem), the mechanical stress level management and optimization of cell oxides and nitrides are in progress.
In NAND technology, the introduction of oxide nitride (ON) scaling technology is one of the important reliability issues. In order to improve the horizontal charge loss of NAND, SK Hynix overcomes by developing a structure such as △DEEP Trap CTN △CTN layer blocked between cells, such as isorate-CTN.
Currently, SK Hynix is developing Compute Express Link (CXL, heterogeneous computing interconnect technology) memory for’ultra-low-power memory’. President Lee emphasized, “In the future, there will be a convergence era in which central processing unit (CPU), storage, and memory are combined like neuromorphic semiconductors,” he said. “There is a need for technology convergence between memory and logic.”
“In the future, semiconductor, artificial intelligence, and communication technologies will converge to become a super-connected era that connects faster with much less power.” “SK hynix provides various solutions for the transmission speed, capacity and strategy required by the ICT society. We will continue to provide it.”
SK hynix is preparing to mass-produce 10 nano-level 4G (1a), and recently succeeded in developing 176-layer 3D NAND.
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