Nepes unveiled a packaging solution that maximizes production efficiency amid the rapid growth of the non-memory semiconductor market.
On the 28th, Nepes announced that it will introduce’nSiP’ as its own semiconductor post-processing technology at the’n-Tech Forum’ held online, and that it will start targeting the global market.
nSiP is a type of system-in-package (SiP), a packaging solution that combines individual chipsets. It features a fan-out package (FOWLP) technology applied directly to a silicon wafer without using a substrate. This provides the advantage of being able to make the size smaller than one-third compared to conventional packaging solutions using substrates and wires.
In particular, Nepes has a panel level package (PLP) process technology that can further maximize production efficiency by using square panels with a size of 600 mm in width and height.
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Nepes said, “The size of the SiP market currently reaches $14.6 billion in 2020, and more than 90% is a traditional method that applies components such as substrates and wires,” said Nepes. Together, the adoption of nSiP based on end-fab technology that can implement high-performance, highly integrated modules is expected to increase.”
Meanwhile, according to market research firm Yol Development, the global SiP market is expected to grow to $18.8 billion in mobile, automotive, and high-performance computing (HPC) areas by 2025.